1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a read circuit capable of directly reading the potential of bit lines in a dynamic random access memory (DRAM).
2. Description of the Related Art
In conventional DRAMs, there is a read circuit composed only of a sense amplifier (a flip-flop circuit) for sensing and restoring data. Such a read circuit is slow in read operation. One reason for this is that the latching of the bit-line potential by the sense-restore sense amplifier involves charging and discharging the bit line of a large capacity, resulting in a slow latching action. Another reason is that causing the read gate to open in synchronization with the sense-restore sense amplifier under the control of the column select signal requires a suitable timing.
In this connection, Published Unexamined Japanese Patent Application No. 1-169798 discloses a bit-line potential direct-read circuit, which reads a small signal read on a bit line from a memory cell immediately after a word line is activated without the intervention of the sense-restore sense amplifier. With this circuit, a read operation in a DRAM can be made faster.
FIG. 11 is a schematic diagram of the circuit disclosed in the above application. For each pair of bit lines BL and BL, there are a sense-restore sense amplifier (a flip-flop circuit FF), a write gate circuit WGT, and a differential read amplifier RA all connected to this bit line pair.
This read amplifier RA is composed of two n-channel metal-oxide silicon field-effect driving transistors (hereinafter, referred to as NMOS transistors) whose respective gates are connected to the bit-line pair, an NMOS transistor for a current source whose gate is supplied with the internal potential V.sub.CC /2 between the power supply potential V.sub.CC and the ground potential V.sub.SS, and two NMOS transistors for read gates which are connected between the two driving NMOS transistors and a pair of read common data lines O and O and are selected by a column select signal CSL. The read common data-line pair O and O, which is connected to a load circuit LD made up of two p-channel MOS FETs (hereinafter, referred to as PMOS transistors), is in common use by a plurality of read amplifiers RA.
In the bit-line potential direct-read method, it is a common practice to separate the read common data-line pair O and O from the write common data-line pair I and I.
FIG. 12 shows the timing of read operation when the memory cell data in the FIG. 11 circuit is a 0.
When the column select signal CSL is activated to open the read gate and then the word line WL is activated, information in the memory cell MC appears on the pair of bit lines BL and BL, which is immediately amplified by the read amplifier RA and then transferred to the pair of common read data lines O and O. This allows data to be read mostly as fast as the static RAM (SRAM). Next, the activating signals SAN and SAP for the sense-restore sense amplifier are activated to enable this sense amplifier SA, which in turn performs a latch action that amplifies the signal on the pair of bit lines BL and BL, or the previously read information, and rewrites it into the memory cell MC. The sense amplifier SA only amplifies and rewrites the signal, so that its operating speed has no effect on the reading speed.
With the conventional bit-line potential direct-read circuit, however, the pattern layout of the integrated circuit makes it difficult to provide the read amplifier RA with a sufficient sensitivity or an amplification factor with less variations. It is desirable that numerous MOS transistors constituting the read amplifiers RA are arranged symmetrically in the direction in which the bit line pair extends. However, squeezing the patterns within the pitch between the pair of bit lines leads to an increased chip size or an imbalanced parasitic resistance.
The most serious problem with such conventional circuits is that high-speed reading cannot be expected especially when a signal to be amplified is small. The reason for this is that a considerable parasitic capacitance of the order of several pF generally existing on the pair of read common data lines O and O makes it difficult for only a single stage of read amplifier RA to amplify a very small input signal under the worst conditions where the potential difference is on the order of 200 mV. In other words, with the conventional bit-line potential direct-read circuit, reading speed varies substantially depending on the magnitude of input signal.